One or more embodiments of the present invention pertain to method and apparatus for checking integrated circuit (IC) designs.
As the size of integrated circuit (IC) features continues to shrink, and the demand for increased circuit density has correspondingly increased, IC designers have been turning to automated design tools, layout tools, and checking tools. Fabrication of ICs is dependent upon the creation of a set of xe2x80x9cmasksxe2x80x9d used during fabrication, where each mask in the set represents a different step in the fabrication (typically an addition or deletion of material). A digitized representation of an image of a mask is commonly called a xe2x80x9cmask layerxe2x80x9d or simply a xe2x80x9clayerxe2x80x9d. Each layer is comprised of a set of geometric shapes representing a desired configuration of materials such as metal, polysilicon, or substrate in a finished IC. For example, layers can represent the deposition of metal, or the etching away of resistive material between two layers of metal so that a xe2x80x9cviaxe2x80x9d is opened.
As is well known, semiconductor physical design follows design rules that are defined, for example, by an integrated circuit manufacturing factory (for example, a foundry) to fabricate the design using a particular manufacturing technology. Thus, design rules are restrictions, or guidelines, within which the design can be implemented so the foundry can use its manufacturing technology to fabricate ICs according to the design. In general, before a layout design of a particular level is transferred onto a photolithography reticle, the design is in the form of a digital computer file, where each of the features has a plurality of associated X and Y coordinates that define their location on a mask. A key task in designing a quality IC is to ensure that the designed features obey the design rules and electrical rules (for example, rules specifying connectivity). For example, and without limitation, design rules checks may identify: (a) layers having a floating metal; (b) devices having a partial gate; (c) metal features with a width larger than a predetermined amount; (d) violations of width, spacing, enclosure, and hole design rules; (e) violations of slot rules; (f) violations of dead zone rules; and (g) special gate rules. Accordingly, because ICs typically comprise a large number features, designers typically employ commercially available software products to perform operations known as xe2x80x9cdesign rule checksxe2x80x9d (DRCs) and/or xe2x80x9celectrical rule checksxe2x80x9d (ERCs). In general, one or more DRCs/ERCs are applied to the features of each layer: (a) directly by measuring their shapes and their relationships to each other, and/or (b) indirectly by creating intermediate layers (also known as xe2x80x9cderived layersxe2x80x9d). Exemplary DRC/ERC processing may include determinations of whether certain minimum interfeature spacings have been violated, whether successive levels are overlapping, and so forth. Derived layers often are more amenable to design rule checking than the original layers, and can be used in the creation of subsequently derived layers.
As is known, a physical computer aided design (xe2x80x9cCADxe2x80x9d) environment is set upxe2x80x94based on design rules and electrical rulesxe2x80x94to implement an IC design, and to check whether the design meets the design and electrical rules. In a DRC/ERC file, DRCs/ERCs often entail generating supplemental features or lines to develop checks that separate one type of feature from others, or that distinguish a real DRC/ERC violation from one that is a false error.
In light of the above, there is a need in the art for method and apparatus for generating such supplemental features and lines that enable a designer to create efficient DRCs/ERCs.
One or more embodiments of the present invention advantageously satisfy the above-identified need in the art. Specifically, one embodiment of the present invention is a method for checking integrated circuit design files using (design rule check)/(electrical rule check) files (DRC/ERC files) wherein design objects are disposed on a grid having a system resolution, the method comprising steps of: (a) growing one or more rectangular boxes having at least two sides of length equal to the system resolution outward or inward from one or more of an edge of a design object and a side of a design object; (b) performing one or more of a spacing DRC/ERC check and an overlay DRC/ERC check; and (c) identifying checks relating to the rectangular boxes.